Posts Tagged ‘FD-SOI technology


Thew new ASIC manufacturer SFARDS is now offering SF3301 sample chips for people interested in building their own miners using the dual-mining SHA-256 and Scrypt ASIC chips. The price is currently set at $200 USD per a pack of 2 SF3301 chips. Alternatively you can also purchase a sample Development board set that includes one dev board with a single SF3301 chip, two power supply boards, radiator and fan at a price of $400 USD. The prices are pretty high and do not include shipping, but do note that these are sample chips and development boards for people that want to test what the SFARDS SF3301 chips are capable of or make their own miners based on the chips. The actual volume prices of the chips and the miners based on them should be lower, or they will be pointless…


Dev Main Board:
– SF3301: 1 chip
– Heatsink: heatsink & 12mmx12mm fan
– FBB Voltage: +/- 0~1.0V
– Communication Interface: RS232 / TTL

Dev Power Supply Board:
– Output Voltage Range: 0.5~1.6V
– Voltage Step: 6.25mV
– Max Current: 120A


It seems that things at SFARDS are progressing well as the company has just released some documents including a datasheet for their upcoming SF3301 Bitcoin and Litecoin dual-mining ASIC chips. The documents include a preliminary power usage report on expected power usage in LTC and BTC mining modes that you can see on the image above. The numbers released in the above tables are higher than what we have anticipated based on previously released information about performance and power usage as the power efficiency numbers were apparently for too low operating voltages and frequencies that are going to be producing too low hashrates to be useable. Also it seems that SFARDS already has some sample chips and will announce pricing details on May 4th as was announced on their official Twitter account.

Official specifications of SFARDS SF3301:
– 160 BTC Units
– 31 LTC Units
– BTC mode up to 80 GH/s with 0.31 W/GH
– LTC mode up to 1.89 MH/s with 2.0 W/MH
– Dual-Mining mode: 100 GH/s BTC and 1.75 MH/s LTC
– Highly integrated with PLL and Pre-Calculation Engine of BTC
– 2-wires UART interface
– Support Crystal and Oscillator
– Fully adjustable clock frequency
– Support body-bias adjust
– On-chip thermal sensor

Based on the official specifications of the SF3301 Dual-Miner chip we are now looking at 100 GHS BTC and 1.75 MHS LTC mining performance per chip with expected power usage of just about 35W. And if we want to overclock it to get about 150 GHS with 3 MHS hashrates it would scale up to about 100W of power usage. Do note that these numbers and specifications are preliminary and are on per chip basis. If we make a 10-chip miner it could turn out to offer 1 THS Bitcoin hashrate and 17.5 MHS Litecoin combined hashrate with a power usage of about 350W which sounds like a pretty reasonable number. However overclocking this to get 1.5 THS and 30 MHS would scale the used power about 3 times all the way up to about 1 KW. So in the end it is going to be all about finding the best balance between hashrate provided and power usage with the maximum performance with overclock definitely not going to be the best option here, but then again the price of the hardware is also going to play a very important role here. People are already placing high hopes on the SF3301 ASIC chips to revive the interest in Litecoin and bring the price to a higher levels as mining for LTC resumes with a more up to date mining hardware that has better power efficiency.

To check out the released technical documents at the official SFARDS GitHub page…


SFARDS, the company formed after the merging Gridseed and WiiBox, has just announced that they have completed their new 28nm SF3301 dual-algorithm ASIC chip manufactured using the latest in FD-SOI processing technology and have released specifications about expected power usage and performance. The SF3301 is the claimed to be the world’s first chip to use this manufacturing process and is at the same time the first 28nm dual-algorithm (SHA-256 and Scrypt) chip, capable of mining these two algorithms simultaneously or separately.

According to SFARDS this technology allows for the ASIC chip to operate at lower voltage while maintaining a higher frequency resulting in better balance between power usage and performance. The SF3301 ASIC chip should have a lowest working voltage of only 0.45V with a BTC power efficiency at 0.19 J/GH, and LTC power efficiency at 1.75 J/MH (better than the initially announced numbers). With a reported performance for a single SF3301 chip for BTC with a hashrate of 152 GH/s, and LTC hashrate of 3.17 MH/s things may become interesting again for Scrypt miners, though it also depends on the price per chip. We are talking about a power consumption figures of about 90W per chip (152 GHS) in BTC mode and about 5.5W per chip (3.17 MHS) in LTC mode or supposedly in dual mining mode, for both BTC and LTC, a combined power usage of about 100W per chip. Now scale that to a 10 chip ASIC miner and you should get something like 1.5 THS BTC + 32 MHS LTC mining power with a 1000W power usage or a bit more…

SFARDS is apparently planning to release a number of documents for the SF3301 as open-source by the end of this month. The ASIC’s development board design and its software should also be published, and in May the design specifications for their debut Dual Miner solution is expected to be released. SFARDS will be selling ASIC development boards and sample chips, making the SF3301 accessible to developers who wish to customize and build their own hardware in the near future, though no mention of expected time frame is mentioned yet. No word yet on piring per chip or the miner or the number of chips we are going to see in the first upcoming miner.

For more information about the new SFARDS ASIC mining hardware manufacturer…